Parallel single-ended buses suffer from high amounts of self-induced noise. This noise occurs from the simultaneous switching of outputs (SSO). The noise is also referred to as SSO noise of simultaneous switching noise (SSN). The noise causes the power supply that circuits operate from to droop and/or overshoot, depending on the di/dt (current switching rate) and the impedance of the power delivery network (PDN). This modulation of the power supply voltage causes circuits to speed-up and slow-down, which reduces timing margins. The noise also couples onto the signals being transmitted and reference voltages, thereby reducing voltage margin.
To reduce the maximum di/dt of a group of wires, the weight of this group of conductors or lanes is monitored, and then an extra signal is introduced that encodes the (logical) polarity of this group of lanes. This is known as “low-weight” bus-invert coding. This form of bus-invert coding reduces the maximum di/dt for a group of lanes by up to 50% and their average current consumption by 18%. It applies where each lane in the group consumes no current for one of the output logic levels (e.g., “0”) and a finite amount of direct current for the other output logic level (e.g., “1”). An example of how the industry uses “low-weight” encoding is in graphics memory interfaces (GDDR) where it is referred to as DBI-DC coding. Implementing DBI-DC requires that an extra bit (i.e., lane) be added to the group of lanes.